Wafer topography often varies significantly from region to region of a semiconductor wafer due to the underlying structure of different height semiconductor components. In an effort to reduce the size of semiconductor devices and thereby improve packing density, it is often necessary to stack one portion of a component on top of another. In those regions of the semiconductor wafer having stacked multi-level components (such as stacked digit lines, stacked capacitors, etc.), an upper surface of a covering insulating layer is elevationally high relative to the substrate. On the other hand, in those regions of the semiconductor wafer in which single level components are constructed, the upper surface of the insulating layer is elevationally low relative to the substrate.
A section of a semiconductor wafer having a varying topography is illustrated in FIG. 1, which shows a semiconductor wafer segment 10 having a first region 12 and a second region 14. Wafer 10 comprises a bulk substrate 16, field oxide 18, and first and second active areas 20, 21 formed between field oxide 18. A p-type impurity is implanted into substrate 16 in first active area 20 of first region 12 to form p region 15. An n-type impurity is implanted into substrate 16 in second active area 21 of second region 14 to for n+ region 17. First conductive runners 22, 24, 26, and 28 are provided on top of field oxide 18 in both first region 12 and second region 14. Second conductive runners 30 and 32 are provided on top of first conductive runners 26 and 28 in second region 14.
An insulative layer 34 having an upper surface 36 is deposited over wafer 10 to cover and protect the semiconductor device. In first region 12, upper surface 36 of insulative layer 34 is at an elevational height "A" relative to substrate 16. A buried contact opening formed in insulative layer 34 at this location is considered to be a comparatively "shallow" contact opening because the insulative layer is relatively thin in first region 12.
In comparison, upper surface 36 of insulative layer 34 is at an elevational height "B" above substrate 16 in second region 14 which is greater than elevational height "A". Upper surface 36 is higher in second region 14 (i.e., height "B") as compared to first region 12 (i.e., height "A") because of the stacked runner structure formed in second region 14. A buried contact opening formed in insulative layer 34 in second region 14 is considered to be a comparatively "deep" contact opening because the insulative layer is relatively thick in this second region.
One example of where this varying topography occurs is in buried digit-line stacked DRAM chips. The stacked conductive runners in second region 14 represent the stacked digit-line structure found in sense amplifiers formed adjacent to, but outside of, a memory array. First region 12 represents other pitched cells which are farther removed from the memory array. In some present stacked DRAM chips, deep buried contacts may have a height "B" equal to approximately two microns, while shallow buried contacts may have a height "A" of approximately one micron or less. This discrepancy between deep and shallow buried contacts on the same wafer introduces significant problems which are illustrated and discussed below with reference to FIGS. 2-5.
In FIG. 2, mask and etching steps were performed on the FIG. 1 wafer to form contact openings 40 and 42. Contact opening 40 has sufficient depth to reach substrate 16 in first active area 20. However, contact opening 42 is "under etched" and does not reach substrate 16 in second active area 21. This "under etch" would result in a defective semiconductor device.
To compensate for this problem, manufacturers are inclined to etch to a greater depth in an effort to insure that contact opening 42 reaches substrate 16. Accordingly, in FIG. 3, an etch is conducted to the FIG. 1 wafer to form contact openings 44 and 46. While contact opening 46 now properly extends to substrate 16 in second active area 21, contact opening 44 can be "over etched" through p region 15 in first active area 20. This "over etch" would also result in a defective semiconductor device.
A separate problem associated with forming buried contact openings is that of misalignment. As shown in FIG. 4, contact opening 48 is misaligned over active area 21 in second region 14. As a result of this misalignment, contact opening 48 is etched into field oxide 18 and through n+ region 17 into substrate 16. Similarly, contact opening 47 is misaligned and etched into field oxide 18 and through p region 15 into substrate 16.
In prior art processes, such misalignment is remedied by one of three solutions illustrated in FIGS. 5A-5C which all include an additional n-type implant processing step. As shown in FIG. 5A, a mask 50 is provided atop insulative layer 34 and patterned to expose contact opening 48 in second region 14. A heavy dose of n-type impurity, typically phosphorous, is implanted through contact opening 48 into substrate 16 to form secondary n+ region 52. Mask 50 prevents the n-type impurity from being implanted through contact opening 47 into p region 15 in first region 12.
A second, more complete, solution is to first mask the p contact regions and perform an n-type implant into the n+ contact regions (as illustrated in FIG. 5A) and then to apply a second mask over the n+ contact regions and perform a p-type implant into the p contact regions as illustrated in FIG. 5B. After first mask 50 is removed, a second mask 51 is provided atop insulative layer 34 and patterned to expose contact opening 47 in first region 12. A p-type impurity, typically boron, is implanted through contact opening 47 into substrate 16 to form secondary p region 53. Mask 51 prevents the p-type impurity from being implanted through contact opening 48 into n+ region 17 in second region 14.
A third solution is to provide a blanket n-type impurity implant across the entire semiconductor wafer as shown in FIG. 5C. The n-type impurity has a lower concentration than that used above with respect to the implant shown in FIG. 5A. This blanket n-type impurity implant forms secondary n region 52 in contact opening 48 of second region 14 as well as slightly degrading p region 15 in first region 12. This prior art solution provides a less-effective plug implant 52 in second region 14, but has the advantage of eliminating additional mask steps that are necessary in the previous solutions.
The present invention defines a process which simultaneously obviates problems associated with varying contact depth and misalignment.